| Periph ID AIC | Symbol | Description |
|---|---|---|
| 18 | (AT91C_ID_AES) | Advanced Encryption Standard 128-bit |
| Function | Description |
|---|---|
| AT91F_AES_CfgPMC | Enable Peripheral clock in PMC for AES |
| Offset | Field | Description |
|---|---|---|
| 0x0 | AES_CR | Control Register |
| 0x4 | AES_MR | Mode Register |
| 0x10 | AES_IER | Interrupt Enable Register |
| 0x14 | AES_IDR | Interrupt Disable Register |
| 0x18 | AES_IMR | Interrupt Mask Register |
| 0x1C | AES_ISR | Interrupt Status Register |
| 0x20 | AES_KEYWxR[4] (AES_KEYWxR) | Key Word x Register |
| 0x40 | AES_IDATAxR[4] (AES_IDATAxR) | Input Data x Register |
| 0x50 | AES_ODATAxR[4] (AES_ODATAxR) | Output Data x Register |
| 0x60 | AES_IVxR[4] (AES_IVxR) | Initialization Vector x Register |
| 0xFC | AES_VR | AES Version Register |
| 0x100 | AES_RPR (PDC_RPR) | Receive Pointer Register |
| 0x104 | AES_RCR (PDC_RCR) | Receive Counter Register |
| 0x108 | AES_TPR (PDC_TPR) | Transmit Pointer Register |
| 0x10C | AES_TCR (PDC_TCR) | Transmit Counter Register |
| 0x110 | AES_RNPR (PDC_RNPR) | Receive Next Pointer Register |
| 0x114 | AES_RNCR (PDC_RNCR) | Receive Next Counter Register |
| 0x118 | AES_TNPR (PDC_TNPR) | Transmit Next Pointer Register |
| 0x11C | AES_TNCR (PDC_TNCR) | Transmit Next Counter Register |
| 0x120 | AES_PTCR (PDC_PTCR) | PDC Transfer Control Register |
| 0x124 | AES_PTSR (PDC_PTSR) | PDC Transfer Status Register |
| Function | Description |
|---|---|
| AT91F_AES_CfgModeReg | Configure the Mode Register of the AES controller |
| AT91F_AES_InputData | Set Input Data x |
| AT91F_AES_SetCryptoKey | Set Cryptographic Key x |
| AT91F_AES_IsInterruptMasked | Test if AES Interrupt is Masked |
| AT91F_AES_GetInterruptMaskStatus | Return AES Interrupt Mask Status |
| AT91F_AES_EnableIt | Enable AES interrupt |
| AT91F_AES_GetOutputData | Get Output Data x |
| AT91F_AES_GetModeReg | Return the Mode Register of the AES controller value |
| AT91F_AES_DisableIt | Disable AES interrupt |
| AT91F_AES_IsStatusSet | Test if AES Status is Set |
| AT91F_AES_GetStatus | Return AES Interrupt Status |
| AT91F_AES_SetInitializationVector | Set Initialization Vector (or Counter) x |
| AT91F_AES_StartProcessing | Start Encryption or Decryption |
| AT91F_AES_SoftReset | Reset AES |
| AT91F_AES_LoadNewSeed | Load New Seed in the random number generator |
| Offset | Name | Description |
|---|---|---|
| 0 | AES_START AT91C_AES_START | Starts Processing 0 = No effect. 1 = Start Encryption/Decryption process. |
| 8 | AES_SWRST AT91C_AES_SWRST | Software Reset 0 = No effect. 1 = Resets the AES. A software triggered hardware reset of the AES interface is performed. |
| 16 | AES_LOADSEED AT91C_AES_LOADSEED | Random Number Generator Seed Loading 0 = No effect. 1 = Loads a new seed in the random number generator used for the different countermeasures. |
| Offset | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | AES_CIPHER AT91C_AES_CIPHER | Processing Mode 0 = Decrypts Data. 1 = Encrypts Data. | ||||||||||||||||||
| 7..4 | AES_PROCDLY AT91C_AES_PROCDLY | Processing Delay Processing Time = 12*(PROCDLY+1) : the Processing Time represents the clock cycles number that the AES needs to perform one encryption/decryption. | ||||||||||||||||||
| 9..8 | AES_SMOD AT91C_AES_SMOD | Start Mode
| ||||||||||||||||||
| 14..12 | AES_OPMOD AT91C_AES_OPMOD | Operation Mode
| ||||||||||||||||||
| 15 | AES_LOD AT91C_AES_LOD | Last Output Data Mode 0 = No effect. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1 = The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions. | ||||||||||||||||||
| 18..16 | AES_CFBS AT91C_AES_CFBS | Cipher Feedback Data Size
| ||||||||||||||||||
| 23..20 | AES_CKEY AT91C_AES_CKEY | Countermeasure Key This field should be written with the value 0xE to allow CTYPE field changes. | ||||||||||||||||||
| 28..24 | AES_CTYPE AT91C_AES_CTYPE | Countermeasure Type Countermeasure type X is disabled (bit set to 0) or enabled (bit set to 1)
|
| Offset | Name | Description |
|---|---|---|
| 0 | AES_DATRDY AT91C_AES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR). |
| 1 | AES_ENDRX AT91C_AES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR. |
| 2 | AES_ENDTX AT91C_AES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR. |
| 3 | AES_RXBUFF AT91C_AES_RXBUFF | PDC Read Buffer Full 0 = AES_RCR or AES_RNCR has a value other than 0. 1 = Both AES_RCR and AES_RNCR has a value of 0. |
| 4 | AES_TXBUFE AT91C_AES_TXBUFE | PDC Write Buffer Empty 0 = AES_TCR or AES_TNCR has a value other than 0. 1 = Both AES_TCR and AES_TNCR has a value of 0. |
| 8 | AES_URAD AT91C_AES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. |
| Offset | Name | Description |
|---|---|---|
| 0 | AES_DATRDY AT91C_AES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR). |
| 1 | AES_ENDRX AT91C_AES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR. |
| 2 | AES_ENDTX AT91C_AES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR. |
| 3 | AES_RXBUFF AT91C_AES_RXBUFF | PDC Read Buffer Full 0 = AES_RCR or AES_RNCR has a value other than 0. 1 = Both AES_RCR and AES_RNCR has a value of 0. |
| 4 | AES_TXBUFE AT91C_AES_TXBUFE | PDC Write Buffer Empty 0 = AES_TCR or AES_TNCR has a value other than 0. 1 = Both AES_TCR and AES_TNCR has a value of 0. |
| 8 | AES_URAD AT91C_AES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. |
| Offset | Name | Description |
|---|---|---|
| 0 | AES_DATRDY AT91C_AES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR). |
| 1 | AES_ENDRX AT91C_AES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR. |
| 2 | AES_ENDTX AT91C_AES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR. |
| 3 | AES_RXBUFF AT91C_AES_RXBUFF | PDC Read Buffer Full 0 = AES_RCR or AES_RNCR has a value other than 0. 1 = Both AES_RCR and AES_RNCR has a value of 0. |
| 4 | AES_TXBUFE AT91C_AES_TXBUFE | PDC Write Buffer Empty 0 = AES_TCR or AES_TNCR has a value other than 0. 1 = Both AES_TCR and AES_TNCR has a value of 0. |
| 8 | AES_URAD AT91C_AES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. |
| Offset | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | AES_DATRDY AT91C_AES_DATRDY | DATRDY 0 = No effect. 1 = En/Dis/Mask/Status of DATRDY (for Manual and Auto Mode in AES_MR). | |||||||||||||||||||||
| 1 | AES_ENDRX AT91C_AES_ENDRX | PDC Read Buffer End 0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR. | |||||||||||||||||||||
| 2 | AES_ENDTX AT91C_AES_ENDTX | PDC Write Buffer End 0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR. | |||||||||||||||||||||
| 3 | AES_RXBUFF AT91C_AES_RXBUFF | PDC Read Buffer Full 0 = AES_RCR or AES_RNCR has a value other than 0. 1 = Both AES_RCR and AES_RNCR has a value of 0. | |||||||||||||||||||||
| 4 | AES_TXBUFE AT91C_AES_TXBUFE | PDC Write Buffer Empty 0 = AES_TCR or AES_TNCR has a value other than 0. 1 = Both AES_TCR and AES_TNCR has a value of 0. | |||||||||||||||||||||
| 8 | AES_URAD AT91C_AES_URAD | Unspecified Register Access Detection 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. | |||||||||||||||||||||
| 14..12 | AES_URAT AT91C_AES_URAT | Unspecified Register Access Type Status Only the last Unspecified Register Access Type is available through the URAT field.
|