PWMC Channel Interface Peripheral

PWMC_CH3 (AT91S_PWMC_CH) 0xFFFCC260 (AT91C_BASE_PWMC_CH3)
SignalSymbolPIO controllerDescription
PWM3(AT91C_PB30_PWM3 )PIOB Periph: B Bit: 30PWM Channel 3
PWM3(AT91C_PB22_PWM3 )PIOB Periph: A Bit: 22PWM Channel 3

FunctionDescription
AT91F_PWMC_CH3_CfgPIOConfigure PIO controllers to drive PWMC_CH3 signals


PWMC_CH2 (AT91S_PWMC_CH) 0xFFFCC240 (AT91C_BASE_PWMC_CH2)
SignalSymbolPIO controllerDescription
PWM2(AT91C_PB21_PWM2 )PIOB Periph: A Bit: 21PWM Channel 2
PWM2(AT91C_PB29_PWM2 )PIOB Periph: B Bit: 29PWM Channel 2

FunctionDescription
AT91F_PWMC_CH2_CfgPIOConfigure PIO controllers to drive PWMC_CH2 signals


PWMC_CH1 (AT91S_PWMC_CH) 0xFFFCC220 (AT91C_BASE_PWMC_CH1)
SignalSymbolPIO controllerDescription
PWM1(AT91C_PB28_PWM1 )PIOB Periph: B Bit: 28PWM Channel 1
PWM1(AT91C_PB20_PWM1 )PIOB Periph: A Bit: 20PWM Channel 1

FunctionDescription
AT91F_PWMC_CH1_CfgPIOConfigure PIO controllers to drive PWMC_CH1 signals


PWMC_CH0 (AT91S_PWMC_CH) 0xFFFCC200 (AT91C_BASE_PWMC_CH0)
SignalSymbolPIO controllerDescription
PWM0(AT91C_PB27_PWM0 )PIOB Periph: B Bit: 27PWM Channel 0
PWM0(AT91C_PB19_PWM0 )PIOB Periph: A Bit: 19PWM Channel 0

FunctionDescription
AT91F_PWMC_CH0_CfgPIOConfigure PIO controllers to drive PWMC_CH0 signals


PWMC_CH Software API (AT91S_PWMC_CH)

OffsetFieldDescription
0x0PWMC_CMRChannel Mode Register
0x4PWMC_CDTYRChannel Duty Cycle Register
0x8PWMC_CPRDRChannel Period Register
0xCPWMC_CCNTRChannel Counter Register
0x10PWMC_CUPDRChannel Update Register
0x14PWMC_Reserved[3] (PWMC_RESERVED)Reserved

PWMC_CH Register Description

PWMC_CH: AT91_REG PWMC_CMR Channel Mode Register

OffsetNameDescription
3..0PWMC_CPRE
AT91C_PWMC_CPRE		Channel Pre-scaler : PWMC_CLKx
ValueLabelDescription
0PWMC_CPRE_MCK
AT91C_PWMC_CPRE_MCK
1PWMC_CPRE_MCK/2
AT91C_PWMC_CPRE_MCK/2
2PWMC_CPRE_MCK/4
AT91C_PWMC_CPRE_MCK/4
3PWMC_CPRE_MCK/8
AT91C_PWMC_CPRE_MCK/8
4PWMC_CPRE_MCK/16
AT91C_PWMC_CPRE_MCK/16
5PWMC_CPRE_MCK/32
AT91C_PWMC_CPRE_MCK/32
6PWMC_CPRE_MCK/64
AT91C_PWMC_CPRE_MCK/64
7PWMC_CPRE_MCK/128
AT91C_PWMC_CPRE_MCK/128
8PWMC_CPRE_MCK/256
AT91C_PWMC_CPRE_MCK/256
9PWMC_CPRE_MCK/512
AT91C_PWMC_CPRE_MCK/512
10PWMC_CPRE_MCK/1024
AT91C_PWMC_CPRE_MCK/1024
11PWMC_CPRE_MCKA
AT91C_PWMC_CPRE_MCKA
12PWMC_CPRE_MCKB
AT91C_PWMC_CPRE_MCKB
8PWMC_CALG
AT91C_PWMC_CALG		Channel Alignment
0: The period is left aligned.
1: The period is center aligned.
9PWMC_CPOL
AT91C_PWMC_CPOL		Channel Polarity
0: The period starts by a low level.
1: The period starts by a high level.
10PWMC_CPD
AT91C_PWMC_CPD		Channel Update Period
0: Writting to the PWMC_CUPDx will notify the duty cycle at the next period start event.
1: Writting to the PWMC_CUPDx will notify the period at the next period start event.

PWMC_CH: AT91_REG PWMC_CDTYR Channel Duty Cycle Register

OffsetNameDescription
31..0PWMC_CDTY
AT91C_PWMC_CDTY		Channel Duty Cycle
Defines the waveform duty cycle. THis value must be defined between 0 and CPRD(PWMC_CPRx).

PWMC_CH: AT91_REG PWMC_CPRDR Channel Period Register

OffsetNameDescription
31..0PWMC_CPRD
AT91C_PWMC_CPRD		Channel Period
If the waveform is left aligned, its period is CPRD*TMCK.
If the waveform is center aligned, its period is 2*CPRD*TMCK.

PWMC_CH: AT91_REG PWMC_CCNTR Channel Counter Register

OffsetNameDescription
31..0PWMC_CCNT
AT91C_PWMC_CCNT		Channel Counter
Internal Counter Value.

PWMC_CH: AT91_REG PWMC_CUPDR Channel Update Register

OffsetNameDescription
31..0PWMC_CUPD
AT91C_PWMC_CUPD		Channel Update
This register is a double buffer for the period or the duty cycle (CUP in PWMC_CMRx).
It prevents from unexpected waveform when modifying waveform period or duty cycle.

PWMC_CH: AT91_REG Reserved Reserved