Description
Source
Call Graph
Start Line: 82
void BOARD_ConfigureSdram(unsigned char busWidth)
{
volatile unsigned int i;
static const Pin pinsSdram = PINS_SDRAM;
volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
unsigned short sdrc_dbw = 0;
switch (busWidth) {
case 16:
sdrc_dbw = AT91C_SDRAMC_DBW_16_BITS;
break;
case 32:
default:
sdrc_dbw = AT91C_SDRAMC_DBW_32_BITS;
break;
}
// Enable corresponding PIOs
PIO_Configure(&pinsSdram, 1);
// Enable EBI chip select for the SDRAM, VDDIOMSEL set: memories are 3.3V powered
WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC | (1 << 16));
// CFG Control Register
WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13
| AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS
| sdrc_dbw
| AT91C_SDRAMC_TWR_2
| AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2
| AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5
| AT91C_SDRAMC_TXSR_8);
for (i = 0; i < 1000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
pSdram[0] = 0x00000000;
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
pSdram[0] = 0x00000000; // Perform PRCHG
for (i = 0; i < 10000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
pSdram[1] = 0x00000001; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
pSdram[2] = 0x00000002; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
pSdram[3] = 0x00000003; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
pSdram[4] = 0x00000004; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
pSdram[5] = 0x00000005; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
pSdram[6] = 0x00000006; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
pSdram[7] = 0x00000007; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
pSdram[8] = 0x00000008; // Perform CBR
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
pSdram[0] = 0x00000000; // Perform Normal mode
}